Semiconductor devices such as, complementary metal oxide semiconductor (CMOS) devices, make extensive use of interconnects and contacts that should be scaleable to allow smooth migration to smaller geometries. Connections to and between active CMOS FET devices are typically created with “silicide” regions wherein a portion of a source/drain region is converted during a thermal treatment into a metallic low resistance region.
Silicide regions are typically formed on active regions and on poly gates. Generally, silicide regions are formed by depositing a refractory metal, such as Titanium (Ti), on the active regions and gates. Heat is applied and the refractory metal reacts with the underlying polysilicon and/or silicon layers by an alloy step forming silicide. Unreacted refractory metal is then removed from the surface of the device. The formed silicide regions provide low resistance regions that can be contacted by metal/conductive interconnects typically formed later.
A common mechanism to form silicide regions involves utilizing Titanium (Ti) as a refractory metal to react with Silicon (Si) to form Titanium-silicide (TiSi2) on gate and active regions. However, TiSi2 has several limitations including, but not limited to, line-width dependent sheet resistance and bridging effect that causes high leakage current.
Another mechanism to form silicide regions employs Cobalt (Co) as a refractory metal to react with Silicon to form Cobalt-silicide (CoSi2). An advantage of CoSi2 over TiSi2 is the extendibility of CoSi2 to smaller CMOS devices. However, formation of Cobalt-silicide can be problematic. For example, cobalt is sensitive to oxygen and water. As a result, formed Cobalt salicide (self aligned silicide) can be contaminated with oxygen and/or water, thereby increasing sheet resistance of the formed Cobalt salicide even if relatively pure inert gas is employed for the heat treatment. One technique employed to reduce this oxidation of cobalt salicide is to form a Titanium (Ti) and/or a Titanium-nitride (TiN) cap layer on top of deposited cobalt prior to its reaction with underlying silicon and/or polysilicon.
Typically, a cobalt layer is deposited on/over a wafer having a top surface comprised of a mixture of exposed surfaces including dielectric surfaces and silicon surfaces. A Ti or TiN cap layer is deposited on the Co layer without exposing the cobalt layer to air. Subsequently, the wafer is subjected to a first annealing process during which the cobalt reacts with silicon at the surface of the wafer where silicon or polysilicon is in contact with the cobalt layer. After the first anneal, the wafer is etched in a NH4OH, H2O2, H2O solution and then with a H2SO4, H2O2, H2O solution. This two-step wet etch process attempts to remove un-reacted cobalt and Ti or TiN. Then, a second anneal is performed to complete the cobalt salicide formation process.
The use of a Ti cap layer has been shown to mitigate oxygen contamination. However, other problems can result from the inclusion of the Ti cap layer in the salicide formation process. For example, Ti can diffuse into the cobalt layer during the first anneal, resulting in mediation of the silicidation reaction by Ti. Thus, the presence of Ti retards the cobalt-silicon reaction so that higher anneal temperatures may be required to complete the reaction. Additionally, some of the Ti can react with cobalt forming an unwanted CoTi inter-metallic mixture layer that causes high sheet resistance. Additionally, the presence of Ti and/or TiN can reduce the amount of cobalt available to react with underlying silicon.